It is known in the art that a delay cell can simply be constructed of a single inverter and a capacitive delay element. Similarly, an entire delay line can be constructed of a chain of inverter delay cells, wherein the output of an inverter delay cell is coupled to the output of the next inverter delay cell. Delay lines are widely used in a great number of integrated circuit applications. They are used, for example, in POR (“Power On Reset”) circuits.
While an inverter delay line can be simply designed and manufactured, and is a cost effective solution for a wide number of applications, such a solution may not be optimum for circuits used in a space environment. A space environment is subject to radiation not found in terrestrial applications that can damage circuits and affect performance. Using a standard inverter delay line circuit in a space environment is not advised because it would be subject to SEGR events (“Single Event Gate Rupture”) and SET events (“Single Event Transients”) if struck with a heavy ion. If the inverter delay line were incorporated into a POR circuit, for example, a SET event could cause the POR circuit to send out a spurious reset signal, which would disrupt the performance of the integrated circuit into which the POR circuit was incorporated. Similarly, a SEGR event could also send out a spurious reset signal, but, in addition, could fatally damage the POR circuit and cause the entire integrated circuit into which the POR circuit was incorporated to become permanently inoperable.
What is desired, therefore, is delay line circuit that is appropriate for use in a POR circuit in a space environment, but is realized with a design that can still be economically implemented in an integrated circuit.